DM9016
3-port switch with Processor Interface
8.12 (Specified config) Register – 14H
Bit
15
14
13
Bit Name
TSTSE1
TSTSE2
Default
0,RW
0,RW
0,RW
Description
Vendor test select control
Vendor test select control
Force Signal Detect
FORCE_TXSD
0: normal SD signal.
1: force SD signal OK in 100M
12
11
FORCE_FEF
PREAMBLEX
0,RW
0,RW
Vendor test select control
Preamble Saving Control
0: when bit 10 is set, the 10M TX preamble count is reduced.
When bit 11 of register 29 is set, 12-bit preamble bit is
reduced; otherwise 22-bit preamble bits is reduced.
1: 10M TX preamble bit count is normal.
10M TX Power Saving Control
1: enable 10M TX power saving
0: disable 10M TX power saving
N-Way Power Saving Control
10
9
TX10M_PWR
NWAY_PWR
1,RW
0,RW
0, RO
1: disable N-Way power saving
0: enable N-Way power saving
Reserved
8
7
Reserved
Read as 0, ignore on write
MDIX_CNTL
MDI/MDIX,RO The polarity of MDI/MDIX value
0: MDI mode
1: MDIX mode
6
5
4
AutoNeg_dpbk
Mdix_fix Value
Mdix_down
0,RW
0, RW
0,RW
Auto-negotiation Loopback
0: normal.
1: test internal digital auto-negotiation Loopback
MDIX_CNTL force value:
When Mdix_down = 1, MDIX_CNTL value depend on the register
value.
MDIX Down
Manual force MDI/MDIX.
0: Enable HP Auto-MDIX
1: Disable HP Auto-MDIX , MDIX_CNTL value depend on 20.5
Vendor monitor select
Vendor monitor select
Reserved
3
2
1
MonSel1
MonSel0
Reserved
0,RW
0,RW
0,RW
Force to 0, in application.
Power down control value
Decision the value of each field Register 19.
0: normal
0
PD_value
0,RW
1: power down
Preliminarydatasheet
DM9016-13-DS-P01
March 26, 2009
59
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
