DM9016
3-port switch with Processor Interface
8.13 DAVICOM Specified Receive Error Counter Register (RECR) – 16H
Bit
Bit Name
Default
Description
15-0
Rcv_ Err_ Cnt
0, RO
Receive Error Counter
Receive error counter that increments upon detection of RXER.
Clean by read this register.
8.14 DAVICOM Specified Disconnect Counter Register (DISCR) – 17H
Bit
Bit Name
Default
Description
15-8
Reserved
0, RO
Reserved
7-0
Disconnect
Counter
0, RO
Disconnect Counter that increment upon detection of
disconnection. Clean by read this register.
8.15 Power Saving Control Register (PSCR) – 1DH
Bit
15-12
11
Bit Name
RESERVED
PREAMBLEX
Default
0,RO
0,RW
Description
RESERVED
Preamble Saving Control
when both bit 10and 11 of register 0x14H are set, the 10M TX
preamble count is reduced.
1: 12-bit preamble bit is reduced.
0: 22-bit preamble bits is reduced.
10
9
AMPLITUDE
TX_PWR
0,RW
0.RW
0,RO
10M TX Amplitude Control Disabled
1: when cable is unconnected with link partner, the TX amplitude is
reduced for power saving.
0: disable TX amplitude reduce function
TX Power Saving Control Disabled
1: when cable is unconnected with link partner, the driving current
of transmit is reduced for power saving.
0: disable TX driving power saving function
RESERVED
8-0
RESERVED
8.16 DAVICOM indirect DATA Register (DATA) – 1EH
Bit
Bit Name
Default
Description
15-0
DATA
0, RW
In-direct DATA register
When write, data to register that addressing by ADDR
When read, data from register that addressing by ADDR
8.17 DAVICOM indirect ADDR Register (ADDR) – 1FH
Bit
Bit Name
Default
Description
15-8
Reserved
0, RO
Reserved
3-0
ADDR
0, RW
In-direct ADDR register
1: addressing to power saving control register (same as REG
1DH)
2: reserved
3: reserved
4: addressing to TX amplitude control register
60
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
