DM9016
3-port switch with Processor Interface
8.7 Auto-negotiation Expansion Register (ANER) - 06H
Bit
Bit Name
Default
Description
15-5
Reserved
0, RO
Reserved
Read as 0, ignore on write
4
3
2
PDF
0, RO/LH
0, RO
Local Device Parallel Detection Fault
PDF = 1: A fault detected via parallel detection function.
PDF = 0: No fault detected via parallel detection function
Link Partner Next Page Able
LP_NP_ABLE = 1: Link partner, next page available
LP_NP_ABLE = 0: Link partner, no next page
Local Device Next Page Able
LP_NP_ABLE
NP_ABLE
0,RO/P
NP_ABLE = 1: DM9016, next page available
NP_ABLE = 0: DM9016, no next page
DM9016 does not support this function, so this bit is always 0
1
0
PAGE_RX
0, RO
0, RO
New Page Received
A new link code word page received. This bit will be automatically
cleared when the register (register 6) is read by management
Link Partner Auto-negotiation Able
LP_AN_ABLE
A “1” in this bit indicates that the link partner supports
Auto-negotiation
8.8 DAVICOM Specified Configuration Register (DSCR) – 10H
Bit
15
Bit Name
BP_4B5B
Default
0,RW
Description
Bypass 4B5B Encoding and 5B4B Decoding
0 = Normal 4B5B and 5B4B operation
1 = 4B5B encoder and 5B4B decoder function bypassed
Bypass Scrambler/Descrambler Function
0 = Normal scrambler and descrambler operation
1 = Scrambler and descrambler function bypassed
Bypass Symbol Alignment Function
0 = Normal operation
14
13
BP_SCR
0, RW
0, RW
BP_ALIGN
1 = Receive functions (descrambler, symbol alignment and symbol
decoding functions) bypassed. Transmit functions (symbol
encoder and scrambler) bypassed
BYPASS ADPOK
12
BP_ADPOK
0, RW
Force signal detector (SD) active. This register is for debug only,
not release to customer
0=Normal operation
1=Forced SD is OK,
11
10
Reserved
TX
RW
Reserved
Force to 0 in application
100BASE-TX Mode Control
1, RW
0 = 100BASE-FX operation
1 = 100BASE-TX operation
9
Reserved
0, RO
Reserved
Preliminarydatasheet
DM9016-13-DS-P01
March 26, 2009
55
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
