DM9016
3-port switch with Processor Interface
8
7
Reserved
F_LINK_100
0, RW
0, RW
Reserved
Force Good Link in 100Mbps
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
6
Reserved
0, RW
Reserved
Force to 0 in application.
5
4
COL_LED
RPDCTR-EN
0, RW
1, RW
COL LED Control (valid in PHY test mode)
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 = Disable automatic reduced power down
1 = Enable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
MF Preamble Suppression Control
3
2
SMRST
MFPSC
0, RW
1, RW
MII frame preamble suppression control bit
0 = MF preamble suppression bit off
1 = MF preamble suppression bit on
1
0
SLEEP
RLOUT
0, RW
0, RW
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loop out Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
56
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
