DM9010
Single Chip Ethernet Controller with General Processor Interface
PDF = 0: No fault detected via parallel detection function
Link Partner Next Page Able
LP_NP_ABLE = 1: Link partner, next page available
LP_NP_ABLE = 0: Link partner, no next page
Local Device Next Page Able
6.3
6.2
LP_NP_ABL
E
0, RO
NP_ABLE
0,RO/P
NP_ABLE = 1: DM9010, next page available
NP_ABLE = 0: DM9010, no next page
DM9010 does not support this function, so this bit is always
0
6.1
6.0
PAGE_RX
0, RO/LH New Page Received
A new link code word page received. This bit will be
automatically cleared when the register (register 6) is read by
management
LP_AN_ABL
E
0, RO
Link Partner Auto-negotiation Able
A “1” in this bit indicates that the link partner supports
Auto-negotiation
8.8 DAVICOM Specified Configuration Register (DSCR) - 16
Bit
16.15
Bit Name
BP_4B5B
Default
0,RW
Description
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and
symbol decoding functions) bypassed. Transmit functions
(symbol encoder and scrambler) bypassed
0 = Normal operation
16.14
16.13
BP_SCR
0, RW
0, RW
BP_ALIGN
16.12 BP_ADPOK
0, RW
BYPASS ADPOK
Force signal detector (SD) active. This register is for debug
only, not release to customer
1=Forced SD is OK,
0=Normal operation
16.11
16.10
Reserved
TX
RW
Reserved
Force to 0 in application
100BASE-TX Mode Control
1, RW
1 = 100BASE-TX operation
16.9
16.8
Reserved
Reserved
0, RO
0, RW
Reserved
Reserved
Force to 0 in application.
Preliminary
38
Version: DM9010-17--DS-P04
Jan. 18, 2006
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
