DM9010
Single Chip Ethernet Controller with General Processor Interface
16.7
16.6
F_LINK_100
Reserved
0, RW
0, RW
Force Good Link in 100Mbps
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
Reserved
Force to 0 in application.
Reserved
Force to 0 in application.
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 = Disable automatic reduced power down
16.5
16.4
Reserved
0, RW
1, RW
RPDCTR-EN
1 = Enable automatic reduced power down
Reset State Machine
16.3
16.2
SMRST
MFPSC
0, RW
1, RW
When writes 1 to this bit, all state machines of PHY will be
reset. This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
16.1
16.0
SLEEP
0, RW
0, RW
Writing a 1 to this bit will cause PHY entering the Sleep
mode and power down all circuit except oscillator and clock
generator circuit. When waking up from Sleep mode (write
this bit to 0), the configuration will go back to the state
before sleep; but the state machine will be reset
Remote Loopout Control
RLOUT
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Bit
Bit Name Default
Description
100M Full Duplex Operation Mode
17.15 100FDX
1, RO
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100M full
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not in
the auto-negotiation mode
17.14 100HDX
1, RO
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
Preliminary
39
Version: DM9010-17--DS-P04
Jan. 18, 2006
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
