DM9010
Single Chip Ethernet Controller with General Processor Interface
bit. If this bit is 1, it means the operation 1 mode is a 100M half
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not in
the auto-negotiation mode
17.13
17.12
10FDX
10HDX
1, RO
1, RO
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M Full
Duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not in
the auto-negotiation mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M half
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not in
the auto-negotiation mode
17.11-17 Reserved
.9
17.8-17. PHYADR
0, RO
1, RW
Reserved
Read as 0, ignore on write
PHY Address Bit 4:0
4
[4:0]
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple
PHY entities must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
written to these bits.
17.3-17. ANMB[3:
0]
0, RO
0
B3 b2 b1 B0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
8.10 10BASE-T Configuration/Status (10BTCSR) - 18
Bit
Bit Name
Default
Description
18.15
Reserved
0, RO
Reserved
Read as 0, ignore on write
18.14
LP_EN
1, RW
Link Pulse Enable
Preliminary
40
Version: DM9010-17--DS-P04
Jan. 18, 2006
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
