DM8203
2-port switch with MII / RMII Interface
8.13 DAVICOM Specified Receive Error Counter Register (RECR) – 16H
Bit
Bit Name
Default
Description
15-0
Rcv_ Err_ Cnt
0, RO
Receive Error Counter
Receive error counter that increments upon detection of RXER.
Clean by read this register.
8.14 DAVICOM Specified Disconnect Counter Register (DISCR) – 17H
Bit
Bit Name
Default
Description
15-8
Reserved
0, RO
Reserved
7-0
Disconnect
Counter
0, RO
Disconnect Counter that increment upon detection of
disconnection. Clean by read this register.
8.15 Power Saving Control Register (PSCR) – 1DH
Bit
15-12
11
Bit Name
RESERVED
PREAMBLEX
Default
0,RO
0,RW
Description
RESERVED
Preamble Saving Control
when both bit 10and 11 of register 14H are set, the 10BASE-T
transmit preamble count is reduced.
1: 12-bit preamble is reduced.
0: 22-bit preamble is reduced.
10
9
AMPLITUDE
TX_PWR
0,RW
0.RW
0,RO
Transmit Amplitude Control Disabled
1: when cable is unconnected with link partner, the TX amplitude is
reduced for power saving.
0: disable Transmit amplitude reduce function
Transmit Power Saving Control Disabled
1: when cable is unconnected with link partner, the driving current
of transmit is reduced for power saving.
0: disable transmit driving power saving function
RESERVED
8-0
RESERVED
42
Preliminary datasheet
DM8203-15-DS-P05
October 23, 2008
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
