DM8203
2-port switch with MII / RMII Interface
9.2 Switch function:
9.2.1 Address Learning
The DM8203 has a self-learning mechanism for
learning the MAC addresses of incoming packets in
real time. DM8203 stores MAC addresses, port
number and time stamp information in the
Hash-based Address Table. It can learn up to 1K
unicast address entry.
The switch engine updates address table with
new entry if incoming packet’s Source Address (SA)
does not exist and incoming packet is valid (non-error
and legal length).
(3). If incoming packet is UNICAST and its
destination port number is equal to source port
number.
9.2.4 Inter-Packet Gap (IPG)
IPG is the idle time between any two valid packets
at the same port. The typical number is 96 bits time.
In other word, the value is 9.6u sec for 10Mbps and
960n sec for 100Mbps.
9.2.5 Back-off Algorithm
Besides, DM8203 has an option to disable
address learning for individual port. This feature can
be set by bit 0 of register 65h
The DM8203 implements the binary exponential
back-off algorithm in half-duplex mode compliant to
IEEE standard 802.3.
9.2.2 Address Aging
9.2.6 Late Collision
The time stamp information of address table is
used in the aging process. The switch engine
updates time stamp whenever the corresponding SA
receives. The switch engine would delete the entry if
its time stamp is not updated for a period of time.
The period can be programmed or disabled through
bit 0 & 1 of register 52h.
Late Collision is a type of collision. If a collision
error occurs after the first 512 bit times of data are
transmitted, the packet is dropped.
9.2.7 Full Duplex Flow Control
The DM8203 supports IEEE standard 802.3x flow
control frames on both transmit and receive sides.
On the receive side, The DM8203 will defer
transmitting next normal frames, if it receives a pause
frame from link partner.
On the transmit side, The DM8203 issues pause
frame with maximum pause time when internal
resources such as received buffers, transmit queue
and transmit descriptor ring are unavailable. Once
resources are available, The DM8203 sends out a
pause frame with zero pause time allows traffic to
resume immediately.
9.2.3 Packet Forwarding
The DM8203 forwards the incoming packet
according to following decision:
(1). If DA is Multicast/Broadcast, the packet is
forwarded to all ports, except to the port on which the
packet was received.
(2). Switch engine would look up address table
based on DA when incoming packets is UNICAST. If
the DA was not found in address table, the packet is
treated as a multicast packet and forward to other
ports. If the DA was found and its destination port
number is different to source port number, the packet
is forward to destination port.
9.2.8 Half Duplex Flow Control
The DM8203 supports half-duplex backpressure.
The inducement is the same as full duplex mode.
When flow control is required, the DM8203 sends jam
pattern and results in a collision.
(3). Switch engine also look up VLAN, Port
Monitor setting and other forwarding constraints for
the forwarding decision, more detail will discuss in
later sections.
The flow control ability can be set in bit 4 of
register 61h.
The DM8203 will filter incoming packets under
following conditions:
(1). Error packets, including CRC errors,
alignment errors, illegal size errors.
(2). PAUSE packets.
44
Preliminary datasheet
DM8203-15-DS-P05
October 23, 2008
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
