DM8203
2-port switch with MII / RMII Interface
8
7
Reserved
0, RW
0, RW
Reserved
Force to 0 in application.
Force Good Link in 100Mbps
F_LINK_100
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
Reserved
Force to 0 in application.
Reserved
6
5
4
Reserved
Reserved
0, RW
0, RW
1, RW
Force to 0 in application.
RPDCTR-EN
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 = Disable automatic reduced power down
1 = Enable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
3
2
SMRST
MFPSC
0, RW
1, RW
1
0
SLEEP
0, RW
0, RW
Reserved
Reserved
Force to 0 in application.
38
Preliminary datasheet
DM8203-15-DS-P05
October 23, 2008
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
