DM8203
2-port switch with MII / RMII Interface
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H
Bit
15
Bit Name
100FDX
Default
1, RO
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M full duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
14
13
12
11
100HDX
10FDX
1, RO
1, RO
1, RO
0, RO
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10HDX
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
Reserved
Reserved
Read as 0, ignore on write
10
9
Reserved
Reserved
0,RW
0,RW
Reserved
Reserved
8-4
PHYADR[4: 0 or 1, RW PHY Address Bit 4:0
0]
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple PHY
entities must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
3-0
ANMB[3:0]
0, RO
These bits are for debug only. The auto-negotiation status will be written
to these bits.
B3 B2 B1 B0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal link ready
Parallel detects signal link ready fail
Auto-negotiation completed successfully
Preliminarydatasheet
DM8203-15-DS-P05
October 23, 2008
39
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
