DS2152
TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING
(WITH ELASTIC STORE ENABLED) Figure 15-10
NOTES:
1. TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored.
2. TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG
will be ignored).
3. TCHBLK is forced to 1 in the same channels where TSER is ignored (see Note 1).
4. The F-bit position for the T1 frame is sampled and passed through the transmit side elastic store
(normally the transmit side formatter overwrites the F-bit position unless the formatter is programmed
to pass-through the F-bit position).
5. TCHCLK does not transition high in the channel in which the data at TSER is ignored (see note 1).
80 of 93
DALLAS [ DALLAS SEMICONDUCTOR ]
