DS2152
RECEIVE SIDE BOUNDARY TIMING
(WITH ELASTIC STORE DISABLED) Figure 15-2
NOTES:
1. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is not enabled (RCR2.5=0).
2. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is enabled (RCR2.5=1).
3. RSYNC in the multiframe mode (RCR2.4=1).
4. ZBTSI mode disabled (RCR2.6=0).
5. RLINK data (FDL bits) is updated 1 bit-time before odd frames and held for two frames.
6. ZBTSI mode is enabled (RCR2.6=1).
7. RLINK data (Z bits) is updated 1 bit-time before odd frames and held for four frames.
8. RLINK and RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled.
RECEIVE SIDE BOUNDARY TIMING
(WITH ELASTIC STORE DISABLED) Figure 15-3
NOTES:
1. RCHBLK is programmed to block channel 24.
2. Shown is RLINK/RLCLK in the ESF framing mode.
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DALLAS [ DALLAS SEMICONDUCTOR ]
