DS2152
TRANSMIT SIDE BOUNDARY TIMING Figure 15-8
NOTES:
1. TSYNC is in the output mode (TCR2.2=1).
2. TSYNC is in the input mode (TCR2.2=0).
3. TCHBLK is programmed to block channel 2.
4. Shown is TLINK/TLCLK in the ESF framing mode.
TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING
(WITH ELASTIC STORE ENABLED) Figure 15-9
NOTES:
1. TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG
will be ignored during channel 24).
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