DS2152
RECEIVE SIDE 1.544 MHz BOUNDARY TIMING
(WITH ELASTIC STORE ENABLED) Figure 15-4
NOTES:
1. RSYNC is in the output mode (RCR2.3=0).
2. RSYNC is in the input mode (RCR2.3=1).
3. RCHBLK is programmed to block channel 24.
RECEIVE SIDE 2.048 MHz BOUNDARY TIMING
(WITH ELASTIC STORE ENABLED) Figure 15-5
NOTES:
1. RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1.
2. RSYNC is in the output mode (RCR2.3=0).
3. RSYNC is in the input mode (RCR2.3=1).
4. RCHBLK is forced to 1 in the same channels as RSER (see Note 1).
5. The F-bit position is passed through the receive side elastic store.
6. RCHCLK does not transition high in the channels in which the RSER data is forced to 1 (see note 1).
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DALLAS [ DALLAS SEMICONDUCTOR ]
