DS2152
FDLS: FDL STATUS REGISTER (Address=01 Hex)
(MSB)
(LSB)
TMEND
RBOC
RPE
RPS
RHALF
RNE
THALF
TNF
SYMBOL
POSITION NAME AND DESCRIPTION
RBOC
RPE
FDLS.7
FDLS.6
Receive BOC Detector Change of State. Set whenever the
BOC detector sees a change of state from a BOC Detected to a
No Valid Code seen or vice versa. The setting of this bit prompt
the user to read the RBOC register for details.
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check complete)
or when the controller has experienced a message fault such as a
CRC checking error, or an overrun condition, or an abort has
been seen. The setting of this bit prompts the user to read the
RPRM register for details.
RPS
RHALF
RNE
FDLS.5
FDLS.4
FDLS.3
FDLS.2
FDLS.1
FDLS.0
Receive Packet Start. Set when the HDLC controller detects an
opening byte. The setting of this bit prompts the user to read the
RPRM register for details.
Receive FIFO Half Full. Set when the receive 16-byte FIFO
fills beyond the halfway point. The setting of this bit prompts the
user to read the RPRM register for details.
Receive FIFO Not Empty. Set when the receive 16-byte FIFO
has at least 1 byte available for a read. The setting of this bit
prompts the user to read the RPRM register for details.
THALF
TNF
Transmit FIFO Half Empty. Set when the transmit 16-byte
FIFO empties beyond the halfway point. The setting of this bit
prompts the user to read the TPRM register for details.
Transmit FIFO Not Full. Set when the transmit 16-byte FIFO
has at least 1 byte available. The setting of this bit prompts the
user to read the TPRM register for details.
TMEND
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this bit
prompts the user to read the TPRM register for details.
NOTE:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
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DALLAS [ DALLAS SEMICONDUCTOR ]
