DS2152
10.2 TRANSMIT SIDE
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR1.7. A 1.544 MHz (CCR1.4=0) or 2.048 MHz (CCR1.4=1) clock can be applied
to the TSYSCLK input. If the user selects to apply a 2.048 MHz clock to the TSYSCLK pin, then the data
input at TSER will be ignored every fourth channel. Hence channels 1, 5, 9, 13, 17, 21, 25, and 29
(timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. The F-bit may be sampled at the MSB of
channel 1. See Figure 15-10. The user must supply an 8 kHz frame sync pulse to the TSSYNC input.
Also, in 2.048 MHz applications the TCHBLK output will be forced high during the channels ignored by
the DS2152. See Section 15 for more details. Controlled slips in the transmit elastic store are reported in
the RIR2.3 bit, and the direction of the slip is reported in the RIR2.5 and RIR2.4 bits.
10.3 MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE
In applications where the DS2152 is connected to backplanes that are frequency-locked to the recovered
T1 clock (i.e., the RCLK output), the full two-frame depth of the onboard elastic stores is really not
needed. In fact, in some delay-sensitive applications the normal two-frame depth may be excessive. If the
CCR3.7 bit is set to 1, then the receive elastic store (and also the transmit elastic store if it is enabled) will
be forced to a maximum depth of 32 bits instead of the normal 386 bits. In this mode, RSYSCLK and
TSYSCLK must be tied together and they must be frequency-locked to RCLK. All of the slip contention
logic in the DS2152 is disabled (since slips cannot occur). Also, since the buffer depth is no longer two
frames deep, the DS2152 must be set up to source a frame pulse at the RSYNC pin and this output must
be tied to the TSSYNC input. On power-up after the RSYSCLK and TSYSCLK signals have locked to
the RCLK signal, the elastic store reset bit (CCR3.6) should be toggled from a 0 to a 1 to insure proper
operation.
11.0 FDL/Fs EXTRACTION AND INSERTION
The DS2152 has the ability to extract/insert data from/into the Facility Data Link (FDL) in the ESF
framing mode and from/into Fs-bit position in the D4 framing mode. Since SLC-96 utilizes the Fs-bit
position, this capability can also be used in SLC-96 applications. The DS2152 contains a complete
HDLC and BOC controller for the FDL and this operation is covered in Section 11.1. To allow for
backward compatibility between the DS2152 and earlier devices, the DS2152 maintains some legacy
functionality for the FDL and this is covered in Section 11.2. Section 11.3 covers D4 and SLC-96
operation. Please contact the factory for a copy of C language source code for implementing the FDL on
the DS2152.
11.1 HDLC AND BOC CONTROLLER FOR THE FDL
11.1.1 General Overview
The DS2152 contains a complete HDLC controller with 16-byte buffers in both the transmit and receive
directions as well as separate dedicated hardware for Bit Oriented Codes (BOC). The HDLC controller
performs all the necessary overhead for generating and receiving Performance Report Messages (PRM)
as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller
automatically generates and detects flags, generates and checks the CRC check sum, generates and
detects abort sequences, stuffs and destuffs 0s (for transparency), and byte-aligns to the FDL data stream.
The 16-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or
transmitted without host intervention. The BOC controller will automatically detect incoming BOC
sequences and alert the host. When the BOC ceases, the DS2152 will also alert the host. The user can set
the device up to send any of the possible 6-bit BOC codes.
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DALLAS [ DALLAS SEMICONDUCTOR ]
