DS2152
RCC1/RCC2/RCC3:
RECEIVE CHANNEL CONTROL REGISTER (Address=1B to 1D Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1 RCC1 (1B)
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
CH9
RCC2 (1C)
RCC3 (1D)
CH17
SYMBOL
POSITION NAME AND DESCRIPTION
CH24
RCC3.7
RCC1.0
Receive Channel 24 Code Insertion Control Bit
0=do not insert data from the RC24 register into the receive data
stream
1=insert data from the RC24 register into the receive data stream
CH1
Receive Channel 1 Code Insertion Control Bit
0=do not insert data from the RC1 register into the receive data
stream
1=insert data from the RC1 register into the receive data stream
9.0 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The
RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low during
individual channels. These outputs can be used to block clocks to a USART or LAPD controller in
Fractional T1 or ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and
TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section
15 for an example.
RCBR1/RCBR2/RCBR3:
RECEIVE CHANNEL BLOCKING REGISTERS (Address=6C to 6E Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
RCBR1 (6C)
RCBR2 (6D)
RCBR3 (6E)
CH17
SYMBOL
POSITION NAME AND DESCRIPTION
CH24
RCBR3.7
Receive Channel Blocking Registers.
0=force the RCHBLK pin to remain low during this channel
time
CH1
RCBR1.0
1=force the RCHBLK pin high during this channel time
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DALLAS [ DALLAS SEMICONDUCTOR ]
