DS2152
RSYNC pin and the signaling data will be re-aligned at the RSER output according to this applied
multiframe boundary. In this mode, the elastic store must be enabled however the backplane clock can be
either 1.544 MHz or 2.048 MHz.
If the signaling reinsertion mode is enabled, the user can control which channels have signaling
reinsertion performed on a channel-by-channel basis by setting the RPCSI control bit high (CCR4.6) and
then programming the RCHBLK output pin to go high in the channels in which the signaling reinsertion
should not occur. If the RPCSI bit is set low, then signaling reinsertion will occur in all channels when
the signaling reinsertion mode is enabled (RSRE=1). How to control the operation of the RCHBLK
output pin is covered in Section 9.
In signaling reinsertion mode, the user has the option to replace all of the extracted robbed-bit signaling
bit positions with 1s. This option is enabled via the RFSA1 control bit (CCR4.5) and it can be invoked on
a per-channel basis by setting the RPCSI control bit (CCR4.6) high and then programming RCHBLK
appropriately just like the per-channel signaling reinsertion operates.
The signaling data in the four-multiframe buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore
TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit
(CCR4.4) should be set high. The user can force a freeze by setting the RFF control bit (CCR4.3) high.
The RSIGF output pin provides a hardware indication that a freeze is in effect. The four-multiframe
buffer provides a three-multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER
pin if RSRE=1). When freezing is enabled (RFE=1), the signaling data will be held in the last known
good state until the corrupting error condition subsides. When the error condition subsides, the signaling
data will be held in the old state for at least an additional 9 ms (or 4.5 ms in D4 framing mode) before
being allowed to be updated with new signaling data.
7.2.2 Transmit Side
Via the THSE control bit (CCR4.2), the DS2152 can be set up to take the signaling data presented at the
TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The
user has the ability to control which channels are to have signaling data from the TSIG pin inserted into
them on a channel-by-channel basis by setting the TPCSI control bit (CCR4.1) high. When TPCSI is
enabled, channels in which the TCHBLK output has been programmed to be set high in, will not have
signaling data from the TSIG pin inserted into them. The hardware signaling insertion capabilities of the
DS2152 are available whether the transmit side elastic store is enabled or disabled. If the elastic store is
enabled, the backplane clock (TSYSCLK) can be either 1.544 MHz or 2.048 MHz.
8.0 PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
The DS2152 can replace data on a channel-by-channel basis in both the transmit and receive directions.
The transmit direction is from the backplane to the T1 line and is covered in Section 8.1. The receive
direction is from the T1 line to the backplane and is covered in Section 8.2.
8.1 TRANSMIT SIDE CODE GENERATION
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the DS2152. The first method which is covered in Section 8.1.1 was a
feature contained in the original DS2151 while the second method, which is covered in Section 8.1.2, is a
new feature of the DS2152.
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DALLAS [ DALLAS SEMICONDUCTOR ]
