51
8Bit Single Chip Microcontroller
DMC73C168
START
(P14.6)
Start
Stop
Cleared by reading ADDATA
READY flag
(P14.7)
144 Machine
cycles
144 Machine
cycles
ANALOG
CHANNEL
Analog
Analog Data
(2)
Analog Data
(3)
Analog Data
(4)
SELECT (P14.0) Data(1)
A/D Converter
operation
Conversion
(1)
Conversion
(2)
Conversion
(3)
Transfer Data
Conversion Data
(1)
Transfer Data
Conversion Data
(2)
ADDATA
(P15)
Previous Conversion Data
Figure 5-9 Continous A/D Conversion
5.7 PLL
The ON-CHIP Phase Locked Loop (PLL) has reference frequency divider, two module prescaler.
4bit swallow counter, 12bit programmable counter. Phase detector and exclusive PLL ports like
VCOH, VCOL, EO1, CO2. Figure 5.7 shows PLL block diagram.
5.7.1 Reference Frequency Divider
The reference frequency divider consists of the crystal oscillator wich has connected external
crystal (4.5MHz). This frequency divider generates 8 kinds of reference frequencies I.e. 1KHz,
5KHz, 6.25KHz, 9KHz, 10KHz, 12.5KHz, 25KHz and 50KHz.
One of reference frequencies can be selected by the program (By setting peripheral file : P16,
bit 5, 4, 3).
5.7.2 PLL Control register
PLL control register are located in the two peripheral registers, P16 and P17. Figure 5-7-1 shows
how to set each bit of PLL control register for PLL lock detection time, Reference frequency and
AM/FM band Mode.
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