SL811HS
7.6.2
I/O Read Cycle
twr
twrrdl
nWR
twasu
twahld
trdp
A0
nRD
tracc
trdhld
trshld
twdsu
twdhld
Register or Memory
Address
D0-D7
nCS
DATA
trcsu
Tcscs *Note
I/O Read Cycle from Register or Memory Buffer
Parameter
Description
Min.
65 ns
65 ns
0 ns
Typ.
Max.
tWR
Write pulse width
Read pulse width
tRD
tWCSU
tWASU
Chip select set-up to nWR
A0 address set-up time
65 ns
10 ns
60 ns
5 ns
tWAHLD
tWDSU
tWDHLD
tRACC
A0 address hold time
Data to Write HIGH set-up time
Data hold time after Write HIGH
Data valid after Read LOW
Data hold after Read HIGH
Chip select LOW to Read LOW
NCS hold after Read HIGH
nCS inactive to nCS *asserted
nWR HIGH to nRD LOW
20 ns
5 ns
25 ns
tRDHLD
tRCSU
0 ns
tRSHLD
0 ns
TCSCS
*
85 ns
85ns
tWRRDL
Note. NCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Time for Auto Inc Mode Reads is
150 ns minimum.
Document #: 38-08008 Rev. *A
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