SL811HS
7.6
Bus Interface Timing Requirements
7.6.1
I/O Write Cycle
twrhigh
twr
nWR
twasu
A0
twahld
twdhld
twdsu
twdsu
twdhld
Register or Memory
Address
DATA
D0-D7
nCS
twshld
twcsu
Tcscs See Note.
I/O Write Cycle to Register or Memory Buffer
Note: nCS an be held LOW for multiple Write cycles provided nWR is cycled.
Parameter
Description
Write pulse width
Min.
65 ns
0 ns
Typ.
Max.
tWR
tWCSU
Chip select set-up to nWR LOW
tWSHLD
Chip select hold time
After nWR HIGH
0 ns
tWASU
A0 address set-up time
A0 address hold time
65 ns
10 ns
60 ns
5 ns
tWAHLD
tWDSU
tWDHLD
tCSCS
Data to Write HIGH set-up time
Data hold time after Write HIGH
nCS inactive to nCS* asserted
NWR HIGH
85 ns
85 ns
tWRHIGH
Write Cycle Time for Auto Inc Mode Writes is 150 ns minimum.
Document #: 38-08008 Rev. *A
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