SL811HS
Bit Position Bit Name
Function
7
SL811HS
Master/Slave
Master = ‘1’
Slave = ‘0’
selection
6
SL811HS D+/D–
Data Polarity Swap ’0’ = no change of polarity (full speed)
’1’ = change polarity (low speed)
5-0
Reserved NA
SOF Low Register, Address [15h]. Read only register
contains the 7 low order bits of Frame Number in positions: bit
7:1. Bit 0 is undefined. Register is updated when a SOF packet
is received. Do not write to this register.
ferred between a peripheral to the SL811HS. The count may
sometimes require up to 16 bits, therefore the count is repre-
sented in two registers: Total Count Low and Total Count High.
EP3 is only supported with DMA operation.
SOF High Register, Address [16h]. Read only register
contains the 4 low order bits of Frame Number in positions: bit
7:4. Bits 3:0 are undefined and should be masked when read by
the user. This register is updated when a SOF packet is received.
The user should not write to this register.
DMA Total Count High Register, Address [36h]. The DMA
Total Count High register contains the high order 8 bits of DMA
count. When written, this register enables DMA if the DMA
Enable bit is set in Control Register 1. The user should always
write Low Count register first, followed by a write to High Count
register, even if high count is 00h.
DMA Total Count Low Register, Address [35h]. The DMA
Total Count Low register contains the low order 8 bits of DMA
count. DMA total count is the total number of bytes to be trans-
Document 38-08008 Rev. *F
Page 19 of 32
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