SL811HS
Control Register 1, Address [05h]. The Control register enables or disables USB transfers and DMA operations with control bits.
Table 28. Control Register 1 [Address 05h]
7
6
5
4
3
2
1
0
Reserved
STBYD
SPSEL
J-K1
J-K0
DMA Dir
DMA Enable USB Enable
Bit Position Bit Name
Function
7
6
Reserved
STBYD
Reserved bit - must be set to '0'.
XCVR Power Control. ‘1’ sets XCVR to low power. For normal operation set this bit to ‘0’.
Suspend mode is entered if bit 6 = ‘1’ and bit ‘0’ (USB Enable) = ‘0’.
5
4
3
SPSEL
Speed Select. ‘0’ selects full speed. ‘1’ selects low speed (also see Table 33 on page 18).
J-K Force State
USB Engine Reset
J-K1 and J-K0 force state control bits are used to generate various USB bus conditions.
Forcing K-state is used for Peripheral device remote wake-up, Resume, and other modes.
These two bits are set to zero on power-up, see Table 12 on page 10 for functions.
2
1
0
DMA Dir
DMA Transfer Direction. Set equal to ‘1’ for DMA READ cycles from SL811HS. Set equal to
‘0’ for DMA WRITE cycles.
DMA Enable
USB Enable
Enable DMA operation when equal to ‘1’. Disable = ‘0’. DMA is initiated when DMA Count
High is written.
Overall Enable for Transfers. ‘1’ enables and’ ‘0 disables. Set this bit to ‘1’ to enable USB
communication. Default at power-up = ‘0’
JK-Force State
USB Engine Reset
Function
0
0
1
1
0
1
0
1
Normal operating mode
Force SE0, D+ and D– are set low
Force K-State, D– set high, D+ set low
Force J-State, D+ set high, D– set low
Interrupt Enable Register, Address [06h] . The SL811HS
provides an Interrupt Request Output that is activated resulting
from a number of conditions. The Interrupt Enable register allows
the user to select events that generate the Interrupt Request
Output assertion. A separate Interrupt Status register is read in
order to determine the condition that initiated the interrupt (see
the description in section Interrupt Status Register, Address
[0Dh]). When a bit is set to ‘1’, the corresponding interrupt is
enabled. Setting a bit in the Interrupt Enable register does not
effect the Interrupt Status register’s value; it just determines
which interrupts are output on INTRQ.
Table 29. Interrupt Enable Register [Address: 06h]
7
6
5
4
3
2
1
0
DMA Status
USB Reset SOF Received DMA Done
Endpoint 3
Done
Endpoint 2
Done
Endpoint 1
Done
Endpoint 0
Done
Bit Position Bit Name
Function
7
DMA Status
When equal to ‘1’, indicates DMA transfer is in progress. When equal to ‘0’, indicates DMA
transfer is complete.
6
5
4
3
2
1
0
USB Reset
Enable USB Reset received interrupt when = ‘1’.
Enable SOF Received Interrupt when = ‘1’.
Enable DMA done Interrupt when = ‘1’.
SOF Received
DMA Done
Endpoint 3 Done
Endpoint 2 Done
Endpoint 1 Done
Endpoint 0 Done
Enable Endpoint 3 done Interrupt when = ‘1’.
Enable Endpoint 2 done Interrupt when = ‘1’.
Enable Endpoint 1 done Interrupt when = ‘1’.
Enable Endpoint 0 done Interrupt when = ‘1’.
Document 38-08008 Rev. *F
Page 17 of 32
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