SL811HS
Table 19. SL811HS Slave Mode Registers
Register Name
Endpoint specific register addresses
EP 0 – A EP 0 - B
EP 1 – A EP 1 - B EP 2 - A EP 2 - B EP 3 - A
EP 3 - B
0x38
EP Control Register
00h
01h
02h
03h
04h
08h
09h
0Ah
0Bh
0Ch
10h
11h
12h
13h
14h
18h
19h
1Ah
1Bh
1Ch
20h
21h
22h
23h
24h
28h
29h
2Ah
2Bh
2Ch
30h
31h
EP Base Address Register
EP Base Length Register
EP Packet Status Register
EP Transfer Count Register
Register Name
0x39
0x32
0x33
0x34
0x3A
0x3B
0x3C
Miscellaneous register addresses
Control Register 1
05h
06h
Interrupt Status Register
Current Data Set Register
Control Register 2
Reserved
0Dh
Interrupt Enable Register
USB Address Register
SOF Low Register (read only)
SOF High Register (read only)
Reserved
0Eh
07h
0Fh
15h
1Dh1Fh
25h-27h
2Dh-2Fh
16h
Reserved
17h
Reserved
DMA Total Count Low Register
DMA Total Count High Register
Reserved
35h
36h
37h
Memory Buffer
40h – FFh
When in slave mode, the registers in the SL811HS are divided
into two major groups. The first group contains Endpoint regis-
ters that manage USB control transactions and data flow. The
second group contains the USB Registers that provide the con-
trol and status information for all other operations.
Endpoints 0–3 Register Addresses
Each endpoint set has a group of five registers that are mapped
within the SL811HS memory. The register sets have address
assignmenEndpoint 0-3 Register Addressests as shown in the
following table.
Endpoint Registers
Table 20. Endpoint 0-3 Register Addresses
Communication and data flow on USB is implemented using
endpoints. These uniquely identifiable entities are the terminals
of communication flow between a USB host and USB devices.
Each USB device is composed of a collection of independently
operating endpoints. Each endpoint has a unique identifier,
which is the Endpoint Number. For more information, see USB
Specification 1.1 section 5.3.1.
Endpoint Register Set
Endpoint 0 – a
Endpoint 0 – b
Endpoint 1 – a
Endpoint 1 – b
Endpoint 2 – a
Endpoint 2 – b
Endpoint 3 – a
Endpoint 3 – b
Address (in Hex)
00 - 04
08 - 0C
10 - 14
18 - 1C
20 - 24
The SL811HS supports four endpoints numbered 0–3. Endpoint
0 is the default pipe and is used to initialize and generically
manipulate the device to configure the logical device as the
Default Control Pipe. It also provides access to the device's
configuration information, allows USB status and control access,
and supports control transfers.
28 - 2C
30 - 34
38 - 3C
For each endpoint set (starting at address Index = 0), the
registers are mapped as shown in the following table.
Endpoints 1–3 support Bulk, Isochronous, and Interrupt
transfers. Endpoint 3 is supported by DMA. Each endpoint has
two sets of registers—the 'A' set and the 'B' set. This allows
overlapped operation where one set of parameters is set up and
the other is transferring. Upon completion of a transfer to an
endpoint, the ‘next data set’ bit indicates whether set 'A' or set 'B'
is used next. The ‘armed’ bit of the next data set indicates
whether the SL811HS is ready for the next transfer without inter-
ruption.
Table 21. Endpoint Register Indices
Endpoint Register Sets
(for Endpoint n starting at register position Index=0)
Index
Endpoint n Control
Endpoint n Base Address
Endpoint n Base Length
Endpoint n Packet Status
Endpoint n Transfer Count
Index + 1
Index + 2
Index + 3
Index + 4
Document 38-08008 Rev. *F
Page 14 of 32
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