SL811HS
Control Register 1 [Address = 05h]. The Control Register 1 enables/disables USB transfer operation with control bits defined as
follows.
Table 11. Control Register 1 [Address 05h]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Suspend
USB Speed J-K state force USB Engine
Reset
Reserved
Reserved
SOF ena/dis
Bit Position Bit Name
Function
7
6
5
4
3
Reserved
‘0’
Suspend
’1’ = enable, ’0’ = disable.
’0’ setup for full speed, ’1’ setup low speed.
See Table 12.
USB Speed
J-K state force
USB Engine Reset USB Engine reset = ’1’. Normal set ’0’.
When a device is detected, the first thing that to do is to send it a USB Reset to force it into
its default address of zero. The USB 2.0 specification states that for a root hub a device
must be reset for a minimum of 50 mS.
2
1
0
Reserved
Reserved
SOF ena/dis
Some existing firmware examples set bit 2, but it is not necessary.
‘0’
’1’ = enable auto Hardware SOF generation; ’0’ = disable.
In the SL811HS, bit 0 is used to enable hardware SOF autogeneration. The generation of
SOFs continues when set to ‘0’, but SOF tokens are not output to USB.
At power-up this register is cleared to all zeros.
There are two cases when communicating with a low speed
device. When a low speed device is connected directly to the
SL811HS, bit 5 of Register 05h is set to ’1’ and bit 6 of register
0Fh, Polarity Swap, is set to ’1’ in order to change the polarity of
D+ and D–. When a low speed device is connected via a HUB to
SL811HS, bit 5 of Register 05h is set to ’0’ and bit 6 of register
0Fh is set to ’0’ in order to keep the polarity of D+ and D– for full
speed. In addition, make sure that bit 7 of USB-A/USB-B Host
Control registers [00h, 08h] is set to ’1’ for preamble generation.
Low-power Modes [Bit 6 Control Register, Address 05h]
When bit 6 (Suspend) is set to ’1’, the power of the transmit
transceiver is turned off, the internal RAM is in suspend mode,
and the internal clocks are disabled.
Note Any activity on the USB bus (that is, K-State, etc.) resumes
normal operation. To resume normal operation from the CPU
side, a Data Write cycle (i.e., A0 set HIGH for a Data Write cycle)
is done. This is a special case and not a normal direct write
where the address is first written and then the data. To resume
normal operation from the CPU side, you must do a Data Write
cycle only.
J-K Programming States [Bits 4 and 3 of Control Register 1,
Address 05h]
The J-K force state control and USB Engine Reset bits are used
to generate a USB reset condition. Forcing K-state is used for
Peripheral device remote wake up, resume, and other modes.
These two bits are set to zero on power-up.
Low Speed/Full Speed Modes [Bit 5 Control Register 1,
Address 05h]
The SL811HS is designed to communicate with either full- or low
speed devices. At power-up bit 5 is LOW, i.e., for full speed.
Table 12. Bus Force States
USB Engine J-K Force
Function
Reset
State
0
0
1
1
0
1
0
1
Normal operating mode
Force USB Reset, D+ and D– are set LOW (SE0)
Force J-State, D+ set HIGH, D– set LOW[2]
Force K-State, D– set HIGH, D+ set LOW[3]
Notes
2. Force K-State for low speed.
3. Force J-State for low speed.
Document 38-08008 Rev. *F
Page 10 of 32
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