CY8C9520A, CY8C9540A
CY8C9560A
Packaging Dimensions
This section illustrates the packaging specifications for the CY8C95xxA device, along with the thermal impedances for each package,
the typical package capacitance on crystal pins, and the solder reflow peak temperature.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 10. 28-Pb (210-Mil) SSOP
51-85079 - *C
Document Number: 38-12036 Rev. *B
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