CY8C24x23A Final Data Sheet
3. Electrical Specifications
2
3.4.8
AC I C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-36. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V
Standard Mode
Min Max
100
Fast Mode
Min Max
Symbol
Description
Units
kHz
Notes
FSCLI2C
SCL Clock Frequency
0
0
400
–
THDSTAI2C Hold Time (repeated) START Condition. After this period, the 4.0
first clock pulse is generated.
–
0.6
µs
TLOWI2C
THIGHI2C
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
1.3
0.6
0.6
0
–
µs
µs
µs
µs
ns
µs
µs
ns
–
TSUSTAI2C Set-up Time for a Repeated START Condition
THDDATI2C Data Hold Time
–
–
100a
0.6
TSUDATI2C Data Set-up Time
250
4.0
4.7
–
–
TSUSTOI2C Set-up Time for STOP Condition
–
TBUFI2C
TSPI2C
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
1.3
0
–
50
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
≥ 250 ns must then be met. This will automatically be the case if
SU;DAT
the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
+ t = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
t
rmax SU;DAT
Table 3-37. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)
Standard Mode
Min Max
100
Fast Mode
Min Max
Symbol
Description
Units
kHz
Notes
FSCLI2C
SCL Clock Frequency
0
–
–
–
–
THDSTAI2C Hold Time (repeated) START Condition. After this period, the 4.0
first clock pulse is generated.
–
µs
TLOWI2C
THIGHI2C
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
µs
µs
µs
µs
ns
µs
µs
ns
TSUSTAI2C Set-up Time for a Repeated START Condition
THDDATI2C Data Hold Time
TSUDATI2C Data Set-up Time
250
4.0
4.7
–
TSUSTOI2C Set-up Time for STOP Condition
TBUFI2C
TSPI2C
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
SDA
SCL
TSPI2C
TLOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Figure 3-9. Definition for Timing for Fast/Standard Mode on the I2C Bus
September 8, 2004
Document No. 38-12028 Rev. *B
39
CYPRESS [ CYPRESS ]
