CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-28. 2.7V AC Digital Block Specifications
Function
Description
Min
Typ
Max
12.7
Units
MHz
Notes
All
Maximum Block Clocking Frequency
2.4V < Vdd < 3.0V.
Functions
Timer
0
0
0
100a
–
–
–
Capture Pulse Width
ns
Maximum Frequency, With or Without Capture
Enable Pulse Width
–
12.7
MHz
ns
0
100a
–
–
–
–
Counter
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
–
–
12.7
12.7
MHz
MHz
Dead Band Kill Pulse Width:
Asynchronous Restart Mode
20
–
–
–
ns
ns
100a
–
0
0
0
Synchronous Restart Mode
Disable Mode0
100a
–
–
–
–
0
ns
Maximum Frequency
–
–
12.7
12.7
MHz
MHz
CRCPRS
Maximum Input Clock Frequency
(PRS Mode)
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
–
–
12.7
6.35
4.23
MHz
MHz
SPIM
SPIS
Maximum data rate at 3.17 MHz due to 2 x over
clocking.
Maximum Input Clock Frequency
ns
ns
100a
–
–
–
–
0
0
Width of SS_ Negated Between Transmissions
Transmitter Maximum Input Clock Frequency
12.7
MHz
Maximum data rate at 1.59 MHz due to 8 x over
clocking.
Receiver
Maximum Input Clock Frequency
–
–
12.7
MHz
Maximum data rate at 1.59 MHz due to 8 x over
clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
September 8, 2004
Document No. 38-12028 Rev. *B
35
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