CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-26. 2.7V AC Operational Amplifier Specifications
Symbol
TROA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
–
–
3.92
µs
Power = Medium, Opamp Bias = High
0.72
µs
TSOA
Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
–
–
5.41
0.72
µs
µs
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
SRROA
SRFOA
BWOA
ENOA
0.31
2.7
–
–
–
–
V/µs
V/µs
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
0.24
1.8
–
–
–
–
V/µs
V/µs
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
0.67
2.8
–
–
–
–
–
–
MHz
Power = Medium, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
MHz
100
nV/rt-Hz
3.4.4
AC Digital Block Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-27. 5V and 3.3V AC Digital Block Specifications
Function
Timer
Description
Min
50a
Typ
Max
Units
ns
Notes
Capture Pulse Width
–
–
Maximum Frequency, No Capture
Maximum Frequency, With Capture
Enable Pulse Width
–
–
–
–
–
49.2
24.6
–
MHz
MHz
ns
4.75V < Vdd < 5.25V.
50a
–
Counter
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
–
–
49.2
24.6
MHz
MHz
4.75V < Vdd < 5.25V.
–
Dead Band Kill Pulse Width:
Asynchronous Restart Mode
20
–
–
–
–
ns
ns
50a
Synchronous Restart Mode
Disable Mode
50a
–
–
–
ns
Maximum Frequency
–
–
49.2
49.2
MHz
MHz
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
–
(PRS Mode)
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
–
24.6
8.2
MHz
MHz
SPIM
SPIS
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
Maximum Input Clock Frequency
–
–
4.1
–
ns
ns
50a
–
Width of SS_ Negated Between Transmissions
Transmitter Maximum Input Clock Frequency
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Receiver
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
September 8, 2004
Document No. 38-12028 Rev. *B
34
CYPRESS [ CYPRESS ]
