CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-21. 2.7V AC Chip-Level Specifications
Symbol
FIMO12
Description
Min
11.5
Typ
Max
Units
MHz
Notes
12.7a,b,c
Internal Main Oscillator Frequency for 12 MHz
12
6
Trimmed for 2.7V operation using factory
trim values. See Figure 3-1b on page 15.
SLIMO Mode = 1.
6.35a,b,c
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
MHz
Trimmed for 2.7V operation using factory
trim values. See Figure 3-1b on page 15.
SLIMO Mode = 1.
CPU Frequency (2.7V Nominal)0
0.930
0
30
3.15a,b
MHz0
FCPU1
12.7a,b,c MHz0
FBLK27
Digital PSoC Block Frequency (2.7V Nominal)
12
Refer to the AC Digital Block Specifica-
tions below.
F32K1
Internal Low Speed Oscillator Frequency
8
32
96
kHz
Jitter32k
TXRST
32 kHz Period Jitter
–
150
–
ns
External Reset Pulse Width
10
–
µs
DC12M
12 MHz Duty Cycle
40
–
50
340
–
60
%
Jitter12M1P
Jitter12M1R
FMAX
12 MHz Period Jitter (IMO) Peak-to-Peak
12 MHz Period Jitter (IMO) Root Mean Squared
Maximum frequency of signal on row input or row output.
ps
–
600
ps
–
–
12.7
MHz
TRAMP
Supply Ramp Time
0
–
–
µs
a. 2.4V < Vdd < 3.0V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for User Modules.
PLL
Enable
T
PLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 3-3. PLL Lock Timing Diagram
PLL
Enable
T
PLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram
September 8, 2004
Document No. 38-12028 Rev. *B
30
CYPRESS [ CYPRESS ]
