CY8C21x34 Final Data Sheet
1. Pin Information
1.1.2
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
20-Pin Part Pinout
Type
Table 1-2. 20-Pin Part Pinout (SSOP)
Digital
IO
IO
IO
IO
Analog
I, M
I, M
I, M
I, M
Power
M
M
M
M
Power
M
M
M
M
Input
I, M
I, M
I, M
I, M
Power
Name
P0[7]
P0[5]
P0[3]
P0[1]
Vss
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Active high external reset with internal
pull down.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
Optional External Clock Input (EXT-
CLK).
I2C Serial Clock (SCL), ISSP-SCLK*.
Ground connection.
I2C Serial Data (SDA), ISSP-SDATA*.
Description
Analog column mux input.
Analog column mux input.
Analog column mux input, integrating
input.
Analog column mux input, integrating
input.
Ground connection.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
CY8C21334 20-Pin PSoC Device
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
Vss
M,I2C SCL,P1[7]
M,I2C SDA, P1[5]
M,P1[3]
M,I2C SCL,P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
SSOP
20
19
18
17
16
15
14
13
12
11
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
XRES
P1[6],M
P1[4], EXTCLK,M
P1[2],M
P1[0],I2C SDA, M
LEGEND
A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Mixed-Signal Array Technical Reference Manual for details.
January 12, 2007
Document No. 38-12025 Rev. *K
9
CYPRESS [ CYPRESS SEMICONDUCTOR ]
