CY8C21x34 Final Data Sheet
1. Pin Information
1.1.3
28-Pin Part Pinout
Table 1-3. 28-Pin Part Pinout (SSOP)
Type
Pin
CY8C21534 28-Pin PSoC Device
Name
Description
No.
Digital Analog
1
2
IO
IO
I, M
I, M
P0[7]
P0[5]
Analog column mux input.
A, I,M, P0[7]
A, I,M, P0[5]
A, I,M, P0[3]
A, I,M, P0[1]
M,P2[7]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vdd
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Analog column mux input and column
output.
P0[6], A,I, M
P0[4], A,I, M
P0[2], A,I, M
P0[0], A,I, M
P2[6],M
3
4
IO
IO
I, M
I, M
P0[3]
P0[1]
Analog column mux input and column
output, integrating input.
Analog column mux input, integrating
input.
M,P2[5]
M, P2[3]
M, P2[1]
P2[4],M
P2[2],M
SSOP
5
IO
IO
IO
IO
M
M
P2[7]
P2[5]
P2[3]
P2[1]
Vss
6
Vss
P2[0],M
XRES
P1[6],M
7
I, M
I, M
Direct switched capacitor block input.
Direct switched capacitor block input.
Ground connection.
M,I2C SCL,P1[7]
M,I2C SDA,P1[5]
M,P1[3]
8
P1[4],EXTCLK,M
P1[2],M
P1[0],I2C SDA,M
9
Power
Power
M,I2C SCL,P1[1]
Vss
10
11
12
13
14
15
16
17
IO
IO
IO
IO
M
M
M
M
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
I2C Serial Clock (SCL), ISSP-SCLK*.
Ground connection.
IO
IO
IO
M
M
M
P1[0]
P1[2]
P1[4]
I2C Serial Data (SDA), ISSP-SDATA*.
Optional External Clock Input (EXT-
CLK).
18
19
IO
M
P1[6]
Input
XRES
Active high external reset with internal
pull down.
20
21
22
23
24
25
26
27
28
IO
IO
IO
IO
IO
IO
IO
IO
I, M
I, M
M
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Direct switched capacitor block input.
Direct switched capacitor block input.
M
I, M
I, M
I, M
I, M
Analog column mux input.
Analog column mux input.
Analog column mux input
Analog column mux input.
Supply voltage.
Power
LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Mixed-Signal Array Technical Reference Manual for details.
January 12, 2007
Document No. 38-12025 Rev. *K
10
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