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CY8C21234-24SXI 参数 Datasheet PDF下载

CY8C21234-24SXI图片预览
型号: CY8C21234-24SXI
PDF下载: 下载PDF文件 查看货源
内容描述: 的PSoC ™混合信号阵列 [PSoC㈢ Mixed-Signal Array]
分类和应用:
文件页数/大小: 42 页 / 564 K
品牌: CYPRESS [ CYPRESS ]
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CY8C21x34 Final Data Sheet  
3. Electrical Specifications  
3.4.7  
AC External Clock Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C  
and are for design guidance only.  
Table 3-24. 5V AC External Clock Specifications  
Symbol  
Description  
Min  
0.093  
Typ  
Max  
24.6  
Units  
MHz  
Notes  
F
Frequency  
High Period  
Low Period  
OSCEXT  
20.6  
20.6  
150  
5300  
ns  
ns  
µs  
Power Up IMO to Switch  
Table 3-25. 3.3V AC External Clock Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
F
F
Frequency with CPU Clock divide by 1  
0.093  
MHz  
Maximum CPU frequency is 12 MHz at 3.3V.  
With the CPU clock divider set to 1, the external  
clock must adhere to the maximum frequency  
and duty cycle requirements.  
12.3  
OSCEXT  
Frequency with CPU Clock divide by 2 or greater  
0.186  
24.6  
MHz  
If the frequency of the external clock is greater  
than 12 MHz, the CPU clock divider must be set  
to 2 or greater. In this case, the CPU clock  
divider will ensure that the fifty percent duty  
cycle requirement is met.  
OSCEXT  
High Period with CPU Clock divide by 1  
Low Period with CPU Clock divide by 1  
Power Up IMO to Switch  
41.7  
41.7  
150  
5300  
ns  
ns  
µs  
Table 3-26. 2.7V AC External Clock Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
0
F
F
Frequency with CPU Clock divide by 1  
0.093  
MHz  
Maximum CPU frequency is 3 MHz at 2.7V.  
With the CPU clock divider set to 1, the external  
clock must adhere to the maximum frequency  
and duty cycle requirements.  
3.08  
OSCEXT  
Frequency with CPU Clock divide by 2 or greater  
0.186  
6.35  
MHz  
If the frequency of the external clock is greater  
than 3 MHz, the CPU clock divider must be set  
to 2 or greater. In this case, the CPU clock  
divider will ensure that the fifty percent duty  
cycle requirement is met.  
OSCEXT  
High Period with CPU Clock divide by 1  
Low Period with CPU Clock divide by 1  
Power Up IMO to Switch  
160  
160  
150  
5300  
ns  
ns  
µs  
January 12, 2007  
Document No. 38-12025 Rev. *K  
29  
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