CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions (continued)
128 100 56 56 56
Name
Type Default
Description
TQFP TQFP SSOP QFN VFBGA
85
70
43
36
7F
PA3 or
WU2
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA3) WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled
by WU2EN bit (WAKEUP.1) and polarity set by
WU2POL (WAKEUP.4). If the 8051 is in suspend and
WU2EN = 1, a transition on this pin starts up the oscil-
lator and interrupts the 8051 to enable it to exit the
suspend mode. Asserting this pin inhibits the chip from
suspending, if WU2EN = 1.
89
90
91
71
72
73
44
45
46
37
38
39
6F
8C
7C
PA4 or
FIFOADR0
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA4) IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave
FIFOs connected to FD[7..0] or FD[15..0].
PA5 or
FIFOADR1
I
Multiplexed pin whose function is selected by:
(PA5) IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave
FIFOs connected to FD[7..0] or FD[15..0].
PA6 or
PKTEND
I
Multiplexed pin whose function is selected by the
(PA6) IFCONFIG[1:0] bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet
data to the endpoint and whose polarity is program-
mable via FIFOPINPOLAR.5.
92
74
47
40
6C
PA7 or
FLAGD or
I/O/Z
I
Multiplexed pin whose function is selected by the
(PA7) IFCONFIG[1:0] and PORTACFG.7 bits.
SLCS#
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status
flag signal.
SLCS# gates all other slave FIFO enable/strobes
Port B
44
34
35
36
37
44
25
26
27
28
29
18
19
20
21
22
3H
4F
4H
4G
5H
PB0 or
FD[0]
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by the
(PB0) following bits: IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
45
46
47
54
PB1 or
FD[1]
I
Multiplexed pin whose function is selected by the
(PB1) following bits: IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
PB2 or
FD[2]
I
Multiplexed pin whose function is selected by the
(PB2) following bits: IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
PB3 or
FD[3]
I
Multiplexed pin whose function is selected by the
(PB3) following bits: IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
PB4 or
FD[4]
I
Multiplexed pin whose function is selected by the
(PB4) following bits: IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
Document #: 38-08032 Rev. *V
Page 24 of 66
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