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CY7C68013A-56BAXCT 参数 Datasheet PDF下载

CY7C68013A-56BAXCT图片预览
型号: CY7C68013A-56BAXCT
PDF下载: 下载PDF文件 查看货源
内容描述: EZ- USB FX2LP USB微控制器,高速USB外设控制器 [EZ-USB FX2LP USB Microcontroller High-Speed USB Peripheral Controller]
分类和应用: 微控制器
文件页数/大小: 66 页 / 909 K
品牌: CYPRESS [ CYPRESS ]
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CY7C68013A, CY7C68014A  
CY7C68015A, CY7C68016A  
Logic Block Diagram  
High performance micro  
using standard tools  
with lower-power options  
24 MHz  
Ext. XTAL  
FX2LP  
I2C  
/0.5  
/1.0  
/2.0  
8051 Core  
x20  
PLL  
Master  
VCC  
1.5k  
12/24/48 MHz,  
four clocks/cycle  
Abundant I/O  
including two USARTs  
Additional I/Os (24)  
connected for  
full speed  
General  
ADDR (9)  
programmable I/F  
to ASIC/DSP or bus  
standards such as  
D+  
D–  
GPIF  
USB  
2.0  
XCVR  
CY  
Smart  
USB  
16 KB  
RAM  
RDY (6)  
CTL (6)  
ATAPI, EPP, etc.  
ECC  
1.1/2.0  
Engine  
Integrated  
full speed and  
high speed  
XCVR  
Up to 96 MBytes/s  
burst rate  
4 kB  
FIFO  
8/16  
Enhanced USB core  
Simplifies 8051 code  
“Soft Configuration”  
Easy firmware changes  
FIFO and endpoint memory  
(master or slave operation)  
Cypress’s EZ-USB® FX2LP(CY7C68013A/14A) is a low  
power version of the EZ-USB FX2(CY7C68013), which is a  
highly integrated, low power USB 2.0 microcontroller. By  
integrating the USB 2.0 transceiver, serial interface engine (SIE),  
enhanced 8051 microcontroller, and a programmable peripheral  
interface in a single chip,  
than USB 2.0 SIE or external transceiver implementations. With  
EZ-USB FX2LP, the Cypress Smart SIE handles most of the  
USB 1.1 and 2.0 protocol in hardware, freeing the embedded  
microcontroller for application specific functions and decreasing  
development time to ensure USB compatibility.  
The General Programmable Interface (GPIF) and Master/Slave  
Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and  
glueless interface to popular interfaces such as ATA, UTOPIA,  
EPP, PCMCIA, and most DSP/processors.  
Cypress has created a cost effective solution that provides  
superior time-to-market advantages with low power to enable  
bus powered applications.  
The ingenious architecture of FX2LP results in data transfer  
rates of over 53 Mbytes per second, the maximum allowable  
USB 2.0 bandwidth, while still using a low cost 8051  
The FX2LP draws less current than the FX2 (CY7C68013), has  
double the on-chip code/data RAM, and is fit, form and function  
compatible with the 56, 100, and 128 pin FX2.  
microcontroller in a package as small as a 56 VFBGA (5 mm x 5  
mm). Because it incorporates the USB 2.0 transceiver, the  
FX2LP is more economical, providing a smaller footprint solution  
Five packages are defined for the family: 56 VFBGA, 56 SSOP,  
56 QFN, 100 TQFP, and 128 TQFP.  
Document #: 38-08032 Rev. *V  
Page 2 of 66  
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