FOR
FOR
enCoRe™ USB CY7C63722/23
CY7C63743
26.0
Switching Characteristics
Parameter
Description
Internal Clock Mode
Internal Clock Frequency
Min.
Max.
Unit
Conditions
FICLK
FICLK2
5.7
5.91
6.3
6.09
MHz
MHz
Internal Clock Mode enabled
Internal Clock Frequency, USB
Internal Clock Mode enabled, Bit 2 of register
mode
0xF8h is set (Precision USB Clocking)[12]
External Oscillator Mode
TCYC
Input Clock Cycle Time
164.2
169.2
ns
USB Operation, with External ±1.5%
Ceramic Resonator or Crystal
TCH
TCL
Clock HIGH Time
Clock LOW Time
0.45 tCYC
0.45 tCYC
ns
ns
Reset Timing
tSTART
tWAKE
tWATCH
Time-out Delay after LVR/BOR
Internal Wake-up Period
WatchDog Timer Period
24
1
10.1
60
5
14.6
ms
ms
ms
Enabled Wake-up Interrupt[13]
FOSC = 6 MHz
USB Driver Characteristics
Transition Rise Time
Transition Rise Time
Transition Fall Time
Transition Fall Time
TR
TR
TF
TF
TRFM
VCRS
75
75
ns
ns
ns
ns
%
V
CLoad = 200 pF (10% to 90%[4]
CLoad = 600 pF (10% to 90%[4]
CLoad = 200 pF (10% to 90%[4]
CLoad = 600 pF (10% to 90%[4]
tr/tf[4, 14]
)
)
)
)
300
300
125
2.0
Rise/Fall Time Matching
80
1.3
Output Signal Crossover
CLoad = 200 to 600 pF[4]
Voltage[18]
USB Data Timing
Low Speed Data Rate
Receiver Data Jitter Tolerance
Receiver Data Jitter Tolerance
Differential to EOP transition Skew
EOP Width at Receiver
Source EOP Width
Differential Driver Jitter
Differential Driver Jitter
Width of SE0 during Diff. Transition
TDRATE
TDJR1
TDJR2
TDEOP
TEOPR2
TEOPT
TUDJ1
TUDJ2
TLST
1.4775
–75
–45
–40
670
1.25
–95
–150
1.5225
75
45
Mb/s Ave. Bit Rate (1.5 Mb/s ±1.5%)
ns
ns
ns
ns
µs
ns
ns
ns
To Next Transition[15]
For Paired Transitions[15]
Note 15
100
Accepts as EOP[15]
1.50
95
150
210
To next transition, Figure 26-5
To paired transition, Figure 26-5
Non-USB Mode Driver
Characteristics
SDATA/SCK Transition Fall Time
Note 16
TFPS2
50
300
ns
CLoad = 150 pF to 600 pF
SPI Timing
SPI Master Clock Rate
SPI Slave Clock Rate
See Figures 26-6 to 26-9[17]
FCLK/3; see Figure 17-1
TSMCK
TSSCK
Notes:
2
2.2
MHz
MHz
12. Initially FICLK2 = FICLK until a USB packet is received.
13. Wake-up time for Wake-up Adjust Bits cleared to 000b (minimum setting)
14. Tested at 200 pF.
15. Measured at cross-over point of differential data signals.
16. Non-USB Mode refers to driving the D–/SDATA and/or D+/SCLK pins with the Control Bits of the USB Status and Control Register, with Control Bit 2 HIGH.
17. SPI timing specified for capacitive load of 50 pF, with GPIO output mode = 01 (medium low drive, strong high drive).
18. Per the USB 2.0 Specification, Table 7.7, Note 10, the first transition from the Idle state is excluded.
Document #: 38-08022 Rev. **
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