FOR
FOR
enCoRe™ USB CY7C63722/23
CY7C63743
23.0
Register Summary
Read/Write/
Both/
Default/
Reset
Address
Register Name
Port 0 Data
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00
0x01
0x02
P0
P1
BBBBBBBB
BBBBBBBB
--RR--RR
00000000
00000000
00000000
Port 1 Data
Port 2 Data
Reserved
D+(SCLK) D- (SDATA)
State State
Reserved
P2.1 (Int Clk VREG Pin
Mode Only
State
0x0A
0x0B
0x0C
0x0D
0x04
0x05
0x06
0x07
GPIO Port 0 Mode 0
GPIO Port 0 Mode 1
GPIO Port 1 Mode 0
GPIO Port 1 Mode 1
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 0 Interrupt Polarity
Port 1 Interrupt Polarity
P0[7:0] Mode0
P0[7:0] Mode1
P1[7:0] Mode0
P1[7:0] Mode1
WWWWWWWW 00000000
WWWWWWWW 00000000
WWWWWWWW 00000000
WWWWWWWW 00000000
WWWWWWWW 00000000
WWWWWWWW 00000000
WWWWWWWW 00000000
WWWWWWWW 00000000
P0[7:0] Interrupt Enable
P1[7:0] Interrupt Enable
P0[7:0] Interrupt Polarity
P1[7:0] Interrupt Polarity
0xF8
Clock Configuration
Ext. Clock
Wake-up Timer Adjust Bit [2:0]
Low-voltage
Reset
Precision
USB
Internal
Clock
External
Oscillator
Enable
BBBBBBBB
00000000
Resume
Delay
Disable
Clocking
Enable
Output
Disable
0x10
0x12
USB Device Address
Device
Address
Enable
Device Address
BBBBBBBB
00000000
EP0 Mode
SETUP
IN
OUT
ACKed
Mode Bit
BBBBBBBB
B--BBBBB
BB--BBBB
00000000
00000000
00000000
Received
Received
Received
Transaction
0x14,
0x16
EP1, EP2 Mode Register
EP0,1, and 2 Counter
STALL
Reserved
ACKed
Mode Bit
Transaction
0x11,
Data 0/1
Toggle
Data Valid
Reserved
Byte Count
0x13,and
0x15
0x1F
USB Status and Control
PS/2 Pull-up
Enable
VREG
Enable
USB
Reset-PS/2
Activity
Reserved
USB Bus
Activity
D+/D- Forcing Bit
BBB-BBBB
00000000
Interrupt
Mode
0x20
0x21
Global Interrupt Enable
Wake-up
Interrupt
Enable
GPIO
Interrupt
Enable
Capture
Capture
SPI
1.024 ms
Interrupt
Enable
128 µs
Interrupt
Enable
USB Bus
Reset-PS/2
Activity Intr.
Enable
BBBBBBBB
-----BBB
00000000
00000000
Timer B Intr. Timer A Intr.
Interrupt
Enable
Enable
Enable
Endpoint Interrupt Enable
Reserved
EP2
EP1
EP0
Interrupt
Enable
Interrupt
Enable
Interrupt
Enable
0x24
0x25
Timer LSB
Timer Bit [7:0]
RRRRRRRR
----RRRR
00000000
00000000
Timer (MSB)
Reserved
Timer Bit [11:8]
0x60
0x61
SPI Data
Data I/O
BBBBBBBB
BBBBBBBB
00000000
00000000
SPI Control
TCMP
TBF
Comm Mode [1:0]
CPOL
CPHA
SCK Select
0x40
0x41
0x42
0x43
0x44
Capture Timer A-Rising,
Data Register
Capture A Rising Data
Capture A Falling Data
Capture B Rising Data
Capture B Falling Data
RRRRRRRR
RRRRRRRR
RRRRRRRR
RRRRRRRR
BBBBBBBB
00000000
00000000
00000000
00000000
00000000
Capture Timer A-Falling,
Data Register
Capture Timer B-Rising,
Data Register
Capture Timer B-Falling,
Data Register
Capture Timer
Configuration
First Edge
Hold
Prescale Bit [2:0]
Capture B
Falling Intr
Enable
Capture B
Rising Intr
Enable
Capture A
Falling Intr
Enable
Capture A
Rising Intr
Enable
0x45
0xFF
Capture Timer Status
Reserved
Capture B
Falling
Capture B
Capture A
Falling
Capture A
----BBBB
00000000
Rising Event
Rising Event
Event
Event
Process Status & Control
IRQ
Watch Dog
Reset
Bus
LVR/BOR
Reset
Suspend
Interrupt
Enable
Sense
Reserved
Run
RBBBBR-B
See
Section
20.0
Pending
Interrupt
Event
Document #: 38-08022 Rev. **
Page 47 of 58
CYPRESS [ CYPRESS ]
