CY7C63001C
CY7C63101C
A maximum of 8 bytes are written into the Endpoint 0 FIFO. If
there are less than 8 bytes of data the CRC is written into the
FIFO.
bitstuffing error) occurred during a SETUP or OUT data phase.
Setting the Stall bit (bit 5) stalls IN and OUT packets. This bit
is cleared whenever a SETUP packet is received by
Endpoint 0. Bit 6 (Data 1/0) must be set to 0 or 1 to select the
DATA packet’s toggle state (0 for DATA0, 1 for DATA1).
Due to register space limitations, the Receive Data Invalid bit
is located in the USB Endpoint 0 TX Configuration Register.
Refer to the Endpoint 0 Transmit section for details. This bit is
set by the SIE if an error is detected in a received DATA packet.
After the transmit data has been loaded into the FIFO, bit 6
should be set according to the data toggle state and bit 7 set
to “1”. This enables the USB Controller to respond to an IN
packet. Bit 7 is cleared and an Endpoint 0 interrupt is
generated by the SIE once the host acknowledges the data
transmission. Bit 7 is also cleared when a SETUP token is
received. The Interrupt Service Routine can check bit 7 to
confirm that the data transfer was successful.
Table 6-4 summarizes the USB Engine response to SETUP
and OUT transactions on Endpoint 0. In the Data Packet
column ‘Error’ represents a packet with a CRC, PID or
bit-stuffing error, or a packet with more than 8 bytes of data.
‘Valid’ is a packet without an Error. ‘Status’ is a packet that is
a valid control read Status stage, while ‘N/Status’ is not a
correct Status stage (see section 6.9.4). The ‘Stall’ bit is
described in Section 6.9.2.2. The ‘StatusOuts’ and
‘EnableOuts’ bits are described in section 6.9.4.
6.9.3
Endpoint 1
Endpoint 1 is capable of transmit only. The data to be trans-
mitted is stored in the 8-byte Endpoint 1 FIFO located at data
memory space 0x78 to 0x7F.
6.9.2.2 Endpoint 0 Transmit
The USB Endpoint 0 TX Register located at I/O address 0x10
controls data transmission from Endpoint 0 (see Figure 6-19).
This is a read/write register. All bits are cleared during reset.
6.9.3.1 Endpoint 1 Transmit
Transmission is controlled by the USB Endpoint 1 TX Register
located at I/O address 0x11 (see Figure 6-20). This is a
read/write register. All bits are cleared during reset.
Bits 0 to 3 indicate the numbers of data bytes to be transmitted
during an IN packet, valid values are 0 to 8 inclusive. Bit 4
indicates that a received DATA packet error (CRC, PID, or
Table 6-4. USB Engine Response to SETUP and OUT Transactions on Endpoint 0
Control Bit Settings Received Packets USB Engine Response
Enable
Token
Type
Data
Toggle
FIFO Write Update
Count
Stall
Status Out
Out
Packet
Update
Interrupt
Yes
Yes
Yes
Yes
No
Reply
ACK
-
-
-
SETUP
SETUP
OUT
Valid
Error
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
-
-
-
None
ACK
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
Valid
1
OUT
Error
None
NAK
0
OUT
Valid
0
OUT
Error
No
No
No
None
STALL
None
ACK
0
OUT
Valid
No
No
No
0
OUT
Error
No
No
No
0
OUT
Status
N/Status
Error
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
0
OUT
STALL
None
0
OUT
b7
INEN
R/W
0
b6
b5
b4
ERR
R/W
0
b3
b2
b1
b0
COUNT0
R/W
DATA1/0
STALL
R/W
0
COUNT3
COUNT2
COUNT1
R/W
0
R/W
0
R/W
0
R/W
0
0
Figure 6-19. USB Endpoint 0 TX Configuration Register (Address 0x10)
b7
INEN
R/W
0
b6
DATA1/0
R/W
b5
STALL
R/W
0
b4
EP1EN
R/W
0
b3
COUNT3
R/W
b2
COUNT2
R/W
b1
COUNT1
R/W
b0
COUNT0
R/W
0
0
0
0
0
Figure 6-20. USB Endpoint 1 TX Configuration Register (Address 0x11)
Document #: 38-08026 Rev. *B
Page 15 of 28
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