CY7C63001C
CY7C63101C
PCB trace capacitance + integrated cable capacitance) must
be less than 250 pF. As Cypress D+/D– transceiver input
capacitance is 20 pF max, up to 230 pF of capacitance is
allowed for in the low speed device’s integrated cable and
PCB. If the cable + PCB capacitance on the D+/D– lines will
be greater than approximately 230 pF, an external 3.3V
regulator must be used as shown in Figure 6-25.
6.11
External USB Pull-Up Resistor
The USB system specifies that a pull-up resistor be connected
on the D– pin of low-speed peripherals as shown in
Figure 6-24. To meet the USB 1.1 spec (section 7.1.6), which
states that the termination must charge the D– line from 0 to
2.0V in 2.5 µs, the total load capacitance on the D+/D– lines
of the low-speed USB device (Cypress device capacitance +
Port0
Port0
Switches,
Devices, Etc.
Switches,
Devices, Etc.
Port1
D+
Port1
VSS
VPP
D–
VCC
XTALOUT
CEXT
XTALIN
7.5kW±1%
+4.35V (min)
For Cext
Wake-up Mode
0.1µF
6-MHz
Resonator
4.7 µF
Figure 6-24. Application Showing 7.5kΩ±1% Pull-Up Resistor
+3.3V
3.3V
Reg
Port0
Port0
Port1
Switches,
Devices, Etc.
Switches,
Devices, Etc.
0.1 µF
Port1
D+
D–
1.5±kW
V
V
SS
PP
V
CEXT
CC
XTALIN
XTALOUT
+4.35V (min.)
For Cext
Wake-up Mode
0.1µF
6-MHz
Resonator
4.7 µF
Figure 6-25. Application Showing 1.5-kΩ±5% Pull-Up Resistor
Document #: 38-08026 Rev. *B
Page 18 of 28
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