CY7C63001C
CY7C63101C
XTALOUT
clk1x
(to USB SIE)
clk2x
(to Microcontroller)
Clock
Doubler
30 pF
30 pF
XTALIN
Figure 2. Clock Oscillator On-chip Circuit
The interrupt controller contains a separate latch for each
6.7
XTALIN/XTALOUT
interrupt. See
Figure 3
for the logic block diagram for the
The XTALIN and XTALOUT pins support connection of a
interrupt controller. When an interrupt is generated, it is
6-MHz ceramic resonator. The feedback capacitors and bias
latched as a pending interrupt. It stays as a pending interrupt
resistor are internal to the IC, as shown in
Figure 2
Leave
until it is serviced or a reset occurs. A pending interrupt only
XTALOUT unconnected when driving XTALIN from an external
generates an interrupt request if it is enabled in the Global
oscillator.
Interrupt Enable Register. The highest priority interrupt
request is serviced following the execution of the current
6.8
Interrupts
instruction.
Interrupts are generated by the General Purpose I/O lines, the
Cext pin, the internal timer, and the USB engine. All interrupts
are maskable by the Global Interrupt Enable Register. Access
to this register is accomplished via IORD, IOWR, and IOWX
instructions to address 0x20. Writing a “1” to a bit position
enables the interrupt associated with that position. During a
reset, the contents of the Interrupt Enable Register are
cleared, disabling all interrupts.
Figure 6-13
illustrates the
format of the Global Interrupt Enable Register.
When servicing an interrupt, the hardware first disables all
interrupts by clearing the Global Interrupt Enable Register.
Next, the interrupt latch of the current interrupt is cleared. This
is followed by a CALL instruction to the ROM address
associated with the interrupt being serviced (i.e., the interrupt
vector). The instruction in the interrupt table is typically a JMP
instruction to the address of the Interrupt Service Routine
(ISR). The user can re-enable interrupts in the interrupt service
routine by writing to the appropriate bits in the Global Interrupt
Enable Register. Interrupts can be nested to a level limited
only by the available stack space.
b3
EP0IE
R/W
0
b2
1024IE
R/W
0
b1
128IE
R/W
0
0
b0
Reserved
b7
CEXTIE
R/W
0
b6
GPIOIE
R/W
0
b5
Reserved
0
b4
EP1IE
R/W
0
Figure 6-13. Global Interrupt Enable Register (GIER - Address 0x20)
128-
µ
s CLR
CLR
Logic 1
128-
µ
s
Interrupt
D
CLK
Q
Enable [1]
128-
µ
s IRQ
1-ms CLR
1-ms IRQ
End P0 CLR
End P0 IRQ
End P1 CLR
End P1 IRQ
GPIO CLR
CLR
CLR
Interrupt
Acknowledge
Logic 1
GPIO
Interrupt
D
CLK
Wake-up CLR
CLR
Logic 1
CEXT
D
CLK
Q
Enable [7]
Wake-up IRQ
Interrupt
Priority
Encoder
Q
GPIO IRQ
Enable [6]
IRQ
Global
Interrupt
Enable
Register
Enable [7:0]
Interrupt
Vector
Figure 3. Interrupt Controller Logic Block Diagram
Document #: 38-08026 Rev. *B
Page 11 of 28
CYPRESS [ CYPRESS SEMICONDUCTOR ]
