CY7C63001C
CY7C63101C
The Program Counter (PC) value and the Carry and Zero flags
(CF, ZF) are automatically stored onto the Program Stack by
the CALL instruction as part of the interrupt acknowledge
process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt.
For example the PUSH A instruction should be used as the
first command in the ISR to save the accumulator value. And,
the IPRET instruction should be used to exit the ISR with the
accumulator value restored and interrupts enabled. The PC,
CF, and ZF are restored when the IPRET or RET instructions
are executed.
1.667 µs. The interrupt latches are sampled at the rising edge
of the last clock cycle in the current instruction.
6.8.2
GPIO Interrupt
The General Purpose I/O interrupts are generated by signal
transitions at the Port 0 and Port 1 I/O pins. GPIO interrupts
are edge sensitive with programmable interrupt polarities.
Setting a bit HIGH in the Port Pull-up Register (see
Figure 6-10 and 6-11) selects a LOW to HIGH interrupt trigger
for the corresponding port pin. Setting a bit LOW activates a
HIGH to LOW interrupt trigger. Each GPIO interrupt is
maskable on a per-pin basis by a dedicated bit in the Port
Interrupt Enable Register. Writing a “1” enables the interrupt.
Figure 6-14 and Figure 6-15 illustrate the format of the Port
Interrupt Enable Registers for Port 0 and Port 1 located at I/O
address 0x04 and 0x05 respectively. These write only
registers are cleared during reset, thus disabling all GPIO
interrupts.
The Interrupt Vectors supported by the USB Controller are
listed in Table 6-3. Interrupt Vector 0 (Reset) has the highest
priority, Interrupt Vector 7 has the lowest priority. Because the
JMP instruction is 2 bytes long, the interrupt vectors occupy 2
bytes.
6.8.1
Interrupt Latency
Interrupt latency can be calculated from the following
equation:
A block diagram of the GPIO interrupt logic is shown in
Figure 6-16. The bit setting in the Port Pull-up Register selects
the interrupt polarity. If the selected signal polarity is detected
on the I/O pin, a HIGH signal is generated. If the Port Interrupt
Enable bit for this pin is HIGH and no other port pins are
requesting interrupts, the OR gate issues a LOW to HIGH
signal to clock the GPIO interrupt flip-flop. The output of the
flip-flop is further qualified by the Global GPIO Interrupt Enable
bit before it is processed by the Interrupt Priority Encoder. Both
the GPIO interrupt flip-flop and the Global GPIO Enable bit are
cleared by on-chip hardware during GPIO interrupt
acknowledge.
Interrupt Latency = (Number of clock cycles remaining in the
current instruction) + (10 clock cycles for
the CALL instruction) + (5 clock cycles
for the JMP instruction)
For example, if a 5-clock-cycle instruction such as JC is being
executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clock
cycles (1+10+5) or a maximum of 20 clock cycles (5+10+5)
after the interrupt is issued. Therefore, the interrupt latency in
this example will be = 20 clock periods = 20 / (12 MHz) =
Table 6-3. Interrupt Vector Assignments
Interrupt Priority
ROM Address
0x00
Function
0 (Highest)
Reset
1
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
128-µs timer interrupt
1.024-ms timer interrupt
USB endpoint 0 interrupt
USB endpoint 1 interrupt
Reserved
2
3
4
5
6
GPIO interrupt
7 (Lowest)
Wake-up interrupt
b7
IE0.7
W
b6
IE0.6
W
b5
IE0.5
W
b4
b3
IE0.3
W
b2
IE0.2
W
b1
b0
IE0.0
W
IE0.4
W
IE0.1
W
0
0
0
0
0
0
0
0
Figure 6-14. Port 0 Interrupt Enable Register (P0 IE - Address 0x04)
b7
IE1.7
W
b6
IE1.6
W
b5
IE1.5
W
b4
IE1.4
W
b3
IE1.3
W
b2
IE1.2
W
b1
IE1.1
W
b0
IE1.0
W
0
0
0
0
0
0
0
0
Figure 6-15. Port 1 Interrupt Enable Register (P1 IE - Address 0x05)
Document #: 38-08026 Rev. *B
Page 12 of 28
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