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CY7C63001C-SXC 参数 Datasheet PDF下载

CY7C63001C-SXC图片预览
型号: CY7C63001C-SXC
PDF下载: 下载PDF文件 查看货源
内容描述: 通用串行总线的微控制器 [Universal Serial Bus Microcontroller]
分类和应用: 微控制器
文件页数/大小: 28 页 / 1077 K
品牌: CYPRESS [ CYPRESS ]
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CY7C63001C  
CY7C63101C  
b7  
b6  
ADR6  
R/W  
0
b5  
ADR5  
R/W  
0
b4  
ADR4  
R/W  
0
b3  
ADR3  
R/W  
0
b2  
ADR2  
R/W  
0
b1  
b0  
ADR0  
R/W  
0
Reserved  
ADR1  
R/W  
0
0
Figure 6-17. USB Device Address Register (USB DA - Address 0x12)  
6.9.1  
USB Enumeration Process  
provides access to the device’s configuration information and  
allows generic USB status and control accesses.  
The USB Controller provides a USB Device Address Register  
at I/O location 0x12. Reading and writing this register is  
achieved via the IORD and IOWR instructions. The register  
contents are cleared during a reset, setting the USB address  
of the USB Controller to 0. Figure 6-17 shows the format of the  
USB Address Register.  
Endpoint 0 can receive and transmit data. Both receive and  
transmit data share the same 8-byte Endpoint 0 FIFO located  
at data memory space 0x70 to 0x77. Received data may  
overwrite the data previously in the FIFO.  
6.9.2.1 Endpoint 0 Receive  
Typical enumeration steps:  
After receiving a packet and placing the data into the Endpoint  
0 FIFO, the USB Controller updates the USB Endpoint 0 RX  
register to record the receive status and then generates a USB  
Endpoint 0 interrupt. The format of the Endpoint 0 RX Register  
is shown in Figure 6-18.  
1. The host computer sends a SETUP packet followed by a  
DATA packet to USB address 0 requesting the Device  
descriptor.  
2. The USB Controller decodes the request and retrieves its  
Device descriptor from the program memory space.  
This is a read/write register located at I/O address 0x14. Any  
write to this register clears all bits except bit 3 which remains  
unchanged. All bits are cleared during reset.  
3. The host computer performs a control read sequence and  
the USB Controller responds by sending the Device  
descriptor over the USB bus.  
Bit 0 is set to 1 when a SETUP token for Endpoint 0 is received.  
Once set to a 1, this bit remains HIGH until it is cleared by an  
I/O write or a reset. While the data following a SETUP is being  
received by the USB engine, this bit is not cleared by an I/O  
write. User firmware writes to the USB FIFOs are disabled  
when bit 0 is set. This prevents SETUP data from being  
overwritten.  
4. After receiving the descriptor, the host computer sends a  
SETUP packet followed by a DATA packet to address 0  
assigning a new USB address to the device.  
5. The USB Controller stores the new address in its USB  
Device Address Register after the no-data control  
sequence completes.  
Bits 1 and 2 are updated whenever a valid token is received  
on Endpoint 0. Bit 1 is set to 1 if an OUT token is received and  
cleared to 0 if any other token is received. Bit 2 is set to 1 if an  
IN token is received and cleared to 0 if any other token is  
received.  
6. The host sends a request for the Device descriptor using  
the new USB address.  
7. The USB Controller decodes the request and retrieves the  
Device descriptor from the program memory.  
8. The host performs a control read sequence and the USB  
Controller responds by sending its Device descriptor over  
the USB bus.  
Bit 3 shows the Data Toggle status of DATA packets received  
on Endpoint 0. This bit is updated for DATA following SETUP  
tokens and for DATA following OUT tokens if Stall (bit 5 of  
0x10) is not set and either EnableOuts or StatusOuts (bits 3  
and 4 of 0x13) are set.  
9. The host generates control reads to the USB Controller to  
request the Configuration and Report descriptors.  
Bits 4 to 7 are the count of the number of bytes received in a  
DATA packet. The two CRC bytes are included in the count,  
so the count value is two greater than the number of data bytes  
received. The count is always updated and the data is always  
stored in the FIFO for DATA packets following a SETUP token.  
The count for DATA following an OUT token is updated if Stall  
(bit 5 of 0x10) is 0 and either EnableOuts or StatusOuts (bits  
3 and 4 of 0x13) are 1. The DATA following an OUT is written  
into the FIFO if EnableOuts is set to 1 and Stall and StatusOuts  
are 0.  
10.The USB Controller retrieves the descriptors from its  
program space and returns the data to the host over the  
USB.  
11.Enumeration is complete after the host has received all the  
descriptors.  
6.9.2  
Endpoint 0  
All USB devices are required to have an endpoint number 0  
that is used to initialize and manipulate the device. Endpoint 0  
b7  
COUNT3  
R/W  
b6  
COUNT2  
R/W  
b5  
COUNT1  
R/W  
b4  
COUNT0  
R/W  
b3  
b2  
IN  
b1  
OUT  
R/W  
0
b0  
SETUP  
R/W  
0
TOGGLE  
R
0
R/W  
0
0
0
0
0
Figure 6-18. USB Endpoint 0 RX Register (Address 0x14)  
Document #: 38-08026 Rev. *B  
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