CY7C1041DV33
Switching Waveforms
(continued)
Figure 5. Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
t
ACE
OE
BHE, BLE
t
DOE
t
LZOE
t
DBE
t
LZBE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
50%
DATA VALID
t
PD
50%
t
HZCE
t
HZBE
t
HZOE
HIGH
IMPEDANCE
IICC
CC
IISB
SB
Figure 6. Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
PWE
WE
t
BW
BHE, BLE
t
SD
DATAI/O
t
HD
t
HA
Notes
22. WE is HIGH for read cycle.
23. Address valid prior to or coincident with CE transition LOW.
24. Data I/O is high impedance if OE or BHE and BLE = V
IH.
25. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05473 Rev. *I
Page 8 of 17
CYPRESS [ CYPRESS SEMICONDUCTOR ]
