CY7C1470V25
CY7C1472V25
CY7C1474V25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The
CY7C1470V25/CY7C1472V25/CY7C1474V25
incorporates a serial boundary scan test access port (TAP). This
port operates in accordance with IEEE Standard 1149.1-1990
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5 V or 1.8 V I/O logic levels.
The CY7C1470V25/CY7C1472V25/CY7C1474V25 contains a
TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
SS
) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to V
DD
through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
0
1
CAPTURE-DR
0
SHIFT-DR
1
EXIT1-DR
0
PAUSE-DR
1
0
EXIT2-DR
1
UPDATE-DR
1
0
0
0
1
0
1
1
SELECT
IR-SCAN
0
CAPTURE-IR
0
SHIFT-IR
1
EXIT1-IR
0
PAUSE-IR
1
EXIT2-IR
1
UPDATE-IR
1
0
0
1
0
1
TDI
Selection
Circuitry
Instruction Register
31 30 29 . . . 2 1 0
S
election
Circuitr
y
TDO
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (V
DD
) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Document Number: 38-05290 Rev. *L
Page 12 of 31
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