CY7C1470V25
CY7C1472V25
CY7C1474V25
Pin Definitions
(continued)
Pin Name
NC(144M,
288M,
576M, 1G)
ZZ
I/O Type
–
Pin Description
These pins are not connected.
They will be used for expansion to the 144M, 288M, 576M and
1G densities.
ZZ “sleep” input.
This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
Input-
asynchronous
Functional Overview
The
CY7C1470V25/CY7C1472V25/CY7C1474V25
are
synchronous-pipelined burst NoBL SRAMs designed specifically
to eliminate wait states during write/read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (t
CO
) is 3.0 ns
(250-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW
[x]
can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Burst Read Accesses
The CY7C1470V25/CY7C1472V25/CY7C1474V25 have an
on-chip burst counter that allows the user the ability to supply a
single address and conduct up to four reads without reasserting
the address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the
section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and will wrap-around when incremented sufficiently.
A HIGH input on ADV/LD will increment the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the address register. The write signals are latched
into the control logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
for
CY7C1474V25,
(DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1470V25 and DQ
a,b
/DQP
a,b
for
CY7C1472V25). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
for
CY7C1474V25,
DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1470V25 & DQ
a,b
/DQP
a,b
for
CY7C1472V25) (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.
The data written during the write operation is controlled by BW
(BW
a,b,c,d,e,f,g,h
for CY7C1474V25, BW
a,b,c,d
for CY7C1470V25
for
CY7C1472V25)
signals.
The
and
BW
a,b
CY7C1470V25/CY7C1472V25/CY7C1474V25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the write enable input (WE) with the selected
byte write select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 2.6 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will tri-state following the next clock rise.
Document Number: 38-05290 Rev. *L
Page 8 of 31
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