CY7C1470V25
CY7C1472V25
CY7C1474V25
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the same
effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
Test Clock
(TCK)
t TMSS
t TH
t TMSH
t
TL
t CYC
2
3
4
5
6
Test Mode Select
(TMS)
t TDIS
t TDIH
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter
Clock
t
TCYC
t
TF
t
TH
t
TL
t
TDOV
t
TDOX
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
TMS hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
5
5
5
–
–
–
ns
ns
ns
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS set-up to TCK clock rise
TDI set-up to TCK clock rise
Capture set-up to TCK rise
50
–
20
20
–
0
5
5
5
–
20
–
–
10
–
–
–
–
ns
MHz
ns
ns
ns
ns
ns
ns
ns
Description
Min
Max
Unit
Output Times
Set-up Times
Notes
9. t
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC Test Conditions. t
R
/t
F
= 1 ns.
Document Number: 38-05290 Rev. *L
Page 14 of 31
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