CY7C1360B
CY7C1362B
CY7C1360B–Pin Definitions
(continued)
Name
V
SSQ
TQFP
3-Chip
Enable
TQFP
2-Chip
Enable
BGA
-
fBGA
-
I/O
I/O Ground
Description
Ground for the I/O circuitry.
5,10,21,26, 5,10,21,26,
55,60,71, 55,60,71,
76
76
V
DDQ
4,11,20,27, 4,11,20,27, A1,F1,J1, C3,C9,D3,
54,61,70, 54,61,70,
M1,U1, D9,E3,E9,F
77
77
A7,F7,J7, 3,F9,G3,
M7,U7
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
31
31
R3
R1
I/O Power
Supply
Power supply for the I/O circuitry.
MODE
Input-
Static
Selects Burst Order.
When tied to GND selects
linear burst sequence. When tied to V
DD
or left
floating selects interleaved burst sequence. This is
a strap pin and should remain static during device
operation. Mode pin has an internal pull-up.
TDO
-
-
U5
P7
JTAG serial
Serial data-out to the JTAG circuit.
Delivers data
on the negative edge of TCK. If the JTAG feature is
output
Synchronous not being utilized, this pin should be disconnected.
This pin is not available on TQFP packages.
JTAG serial
Serial data-In to the JTAG circuit.
Sampled on the
rising edge of TCK. If the JTAG feature is not being
input
Synchronous utilized, this pin can be disconnected or connected
to V
DD
. This pin is not available on TQFP packages.
JTAG serial
Serial data-In to the JTAG circuit.
Sampled on the
input
rising edge of TCK. If the JTAG feature is not being
Synchronous utilized, this pin can be disconnected or connected
to V
DD
. This pin is not available on TQFP packages.
JTAG-Clock
Clock input to the JTAG circuitry.
If the JTAG
feature is not being utilized, this pin must be
connected to V
SS
. This pin is not available on TQFP
packages.
-
No Connects.
Not internally connected to the die
TDI
-
-
U3
P5
TMS
-
-
U2
R5
TCK
-
-
U4
R7
NC
14,16,66,
42,39,38
B1,C1,
14,16,38,
39,42,43, R1,T1,T2,
J3,D4,
66,
L4,5J,5R,
6T,6U,
B7,C7,
R7
A11,B1,C2,
C10,H1,H3,
H9,H10,
N2,N5,N7,
N10,P1,A1,
B11,P2,R2,
N6
Document #: 38-05291 Rev. *C
Page 8 of 34
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