CY7C1360B
CY7C1362B
CY7C1360B–Pin Definitions
(continued)
Name
ADSP
TQFP
3-Chip
Enable
84
TQFP
2-Chip
Enable
84
BGA
A4
fBGA
B9
I/O
Description
Input-
Address Strobe from Processor, sampled on
Synchronous
the rising edge of CLK, active LOW.
When
asserted LOW, addresses presented to the device
are captured in the address registers. A
1
, A
0
are
also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE
1
is deasserted HIGH.
Input-
Address Strobe from Controller, sampled on the
Synchronous
rising edge of CLK, active LOW.
When asserted
LOW, addresses presented to the device are
captured in the address registers. A
1
, A
0
are also
loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
Input-
Asynchro-
nous
ZZ “Sleep” Input, active HIGH.
When asserted
HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
ADSC
85
85
B4
A8
ZZ
64
64
T7
H11
DQs,
DQPs
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,7,
8,9,12,13,1
8,19,22,
23,24,25,
28,29,51,
80,1,30
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,7,
8,9,12,13,1
8,19,22,
23,24,25,
28,29,51,
80,1,30
K6,L6,
M6,N6,
K7,L7,
N7,P7,
E6,F6,
G6,H6,
D7,E7,
G7,H7,
D1,E1,
G1,H1,
E2,F2,
G2,H2,
K1,L1,
N1,P1,
K2,L2,
M2,N2,
P6,D6,
D2,P2
I/O-
Bidirectional Data I/O lines.
As inputs, they feed
M11,L11,
K11,J11, Synchronous into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data
J10,K10,
contained in the memory location specified by the
L10,M10,
addresses presented during the previous clock rise
D10,E10,
F10,G10,
of the read cycle. The direction of the pins is
D11,E11,
controlled by OE. When OE is asserted LOW, the
F11,G11,
pins behave as outputs. When HIGH, DQs and
D1,E1,F1,
DQP
X
are placed in a three-state condition.
G1,D2,E2,
F2,G2,J1,
K1,L1,M1,
J2,K2,L2,
M2,N11,
C11,C1,N1
V
DD
15,41,65,
91
15,41,65,
91
J2,C4,J4, D4,D8,E4, Power Supply
Power supply inputs to the core of the device.
R4,J6
E8,F4,F8,
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
D3,E3,
F3,H3,
K3,M3,
N3,P3,
D5,E5,
F5,H5,
K5,M5,
N5,P5
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
E6,E7,F5,
F6,F7,G5,
G6,G7,H2,
H5,H6,H7,J
5,J6,J7,
K5,K6,K7,
L5,L6,L7,
M5,M6,M7,
N4,N8
Ground
Ground for the core of the device.
V
SS
17,40,67,
90
17,40,67,
90
Document #: 38-05291 Rev. *C
Page 7 of 34
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