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CY7C1061AV33-10ZXI 参数 Datasheet PDF下载

CY7C1061AV33-10ZXI图片预览
型号: CY7C1061AV33-10ZXI
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 1M ×16 )静态RAM [16-Mbit (1M x 16) Static RAM]
分类和应用: 内存集成电路静态存储器光电二极管
文件页数/大小: 10 页 / 642 K
品牌: CYPRESS [ CYPRESS ]
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CY7C1061AV33  
Switching Waveforms (continued)  
Write Cycle No. 1 (CE1 or CE2 Controlled) [15, 16]  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tSA  
tAW  
tHA  
tPWE  
WE  
BHE/BLE  
OE  
tBW  
tHD  
tSD  
VALID DATA  
DATA IO  
NOTE 17  
tHZOE  
Write Cycle No. 2 (WE Controlled, OE LOW) [15, 16]  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tBW  
BHE/BLE  
tAW  
tHA  
tSA  
tPWE  
WE  
tSD  
VALID DATA  
tHD  
NOTE 17  
DATA IO  
tLZWE  
tHZWE  
Notes  
15. Data IO is high impedance if OE, or BHE or BLE or both = V  
.
IH  
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.  
1
17. During this period, the IOs are in output state and input signals should not be applied.  
Document #: 38-05256 Rev. *G  
Page 6 of 10  
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